The present disclosure relates generally to a semiconductor structure and more particularly relates to an in-situ sealing structure on an interposer.
Performance requirements such as increased bandwidth, reduced latency, and lower power are driving the adoption of 3D-IC designs, and thus silicon interposers. An interposer is an electrical interface to spread a connection to a wider pitch or to reroute a connection to a different connection. Silicon interposers are being used to stack chips side-by-side, allowing designers to put dies next to each other in a high-bandwidth and low-latency configuration. A common example of an interposer is an integrated circuit die to Ball Grid Array (BGA). This is done through various substrates, both rigid and flexible. While more pillars are required in the interposer, the dimension of the surface of the substrate of the interposer for arranging the pillars gets larger. Also, the patterns of the pillars get more complicated, and the heights of the pillars will vary because of the pattern densities of the arrangements of the pillars in different areas. The failed joints may happen between the lower pillars of the interposer and vias of a connected device while the heights of the pillars are different. To solve the failed joints, the flux may be required to be jetted on the pillars to facilitate coupling the pillars of the interposer with vias of the connected device. However, the jetted flux tends to creep onto the alignment mark and cause machine continuous recognition fail and lower down throughput.
Therefore, there is a requirement for the present disclosure concerning the process method for in-situ plating a seal wall around alignment mark to prevent from the coverage of the flux. This seal wall can be plated with pillars at the same time, and increase limited manufacturing cost.